The present invention relates to a method for manufacturing a non-volatile memory device and a method for manufacturing a semiconductor device including the non-volatile memory device, and more particularly to a method for manufacturing a non-volatile memory device having a plurality of charge storage regions for each word gate, and a method for manufacturing a semiconductor device including the non-volatile memory device.
Non-volatile semiconductor memory devices include a MONOS (Metal Oxide Nitride Oxide Semiconductor) type and a SONOS (Silicon Oxide Nitride Oxide Silicon) type in which a gate dielectric layer between a channel region and a control gate is composed of a stacked layered body of a silicon oxide layerxe2x80x94a silicon nitride layerxe2x80x94a silicon oxide layer, wherein a charge is trapped in the silicon nitride layer.
One known MONOS type non-volatile memory device is shown in FIG. 22, (Y. Hayashi, et al, 2000 Symposium on VLSI Technology Digest of Technical Papers p.122-p.123).
The MONOS type memory cell 100 has a word gate 14 formed over a semiconductor substrate 10 through a first gate dielectric layer 12. Also, a first control gate 20 and a second control gate 30 in the form of sidewalls are disposed on both sides of the word gate 14. A second gate dielectric layer 22 is present between a bottom section of the first control gate 20 and the semiconductor substrate 10, and a dielectric layer 24 is present between a side surface of the first control gate 20 and the word gate 14. Similarly, a second gate dielectric layer 22 is present between a bottom section of the second control gate 30 and the semiconductor substrate 10, and a dielectric layer 24 is present between a side surface of the second control gate 30 and the word gate 14. Impurity layers 16 and 18 that each compose a source region or a drain region are formed in the semiconductor substrate 10 between the opposing control gates 20 and 30 of adjacent memory cells.
In this manner, each memory cell 100 includes two MONOS type memory elements on the side surfaces of the word gate 14. Also, these two MONOS type memory elements are independently controlled. Therefore, a single memory cell 100 can store 2-bit information.
In view of the foregoing, one object of the present invention is to provide a method for manufacturing a MONOS type non-volatile memory device having a plurality of charge storing regions and a method for manufacturing a semiconductor device including the non-volatile memory device.
A method for manufacturing a semiconductor device including a non-volatile memory device, and a resistance element including a resistance conductive layer in accordance with an embodiment of the present invention comprises the following. A first dielectric layer is formed above a semiconductor layer and a first conductive layer is formed above the first dielectric layer. A second dielectric layer is formed above a portion of the first conductive layer that becomes the resistance conductive layer. A stopper layer is formed above the first conductive layer and the second dielectric layer. The stopper layer and the first conductive layer are patterned to form a gate layer. The stopper layer, the second dielectric layer and the first conductive layer are patterned to form the resistance conductive layer Sidewall-like control gates are formed through an ONO film on both side surfaces of the gate layer. A third dielectric layer is formed above the gate layer and the resistance conductive layer. The third dielectric layer is polished such that the stopper layer is exposed and then the stopper layer is removed. A second conductive layer is formed above the gate layer and the resistance conductive layer. The second conductive layer is then patterned to form a word line. Finally, the gate layer is patterned to form a word gate.
A method for manufacturing a semiconductor device including a non-volatile memory device, and a resistance element including a resistance conductive layer in accordance with another embodiment of the present invention comprises the following. A first dielectric layer is formed above a semiconductor layer and a first conductive layer is formed above the first dielectric layer. A stopper layer is formed above the first conductive layer. The stopper layer and the first conductive layer are patterned to form a gate layer and the resistance conductive layer. Sidewall-like control gates are formed through an ONO film on both side surfaces of the gate layer The stopper layer formed above the resistance conductive layer is then removed. A second dielectric layer is formed above at least the resistance conductive layer. A third dielectric layer is formed above the gate layer and the resistance conductive layer. The third dielectric layer is then polished such that the stopper layer is exposed, and the second dielectric layer formed above the resistance conductive layer remains. The stopper layer is then removed. A second conductive layer is formed above the gate layer and the resistance conductive layer. Next, the second conductive layer is patterned to form a word line. Finally, the gate layer is patterned to form a word gate.